FABRICATION OF AN EEPROM CELL WITH SiGe SOURCE/DRAIN REGIONS

ABSTRACT

An EEPROM memory cell uses silicon-germanium/silicon and emitter polysilicon film for fabricating shallow source/drain regions to increase a breakdown voltage with respect to a well. The source/drain regions are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage of a well in a bipolar process is approximately 10 volts. Due to the increased breakdown voltage achieved, EEPROM memory cells can be produced along with bipolar devices on a single integrated circuit chip and fabricated on a common semiconductor fabrication line.

CROSS-REFERENCE TO RELATED APPLICATION

This is a divisional of pending U.S. patent application Ser. No.10/887,990, filed Jul. 9, 2004.

TECHNICAL FIELD

The present intention relates to integrated circuit fabrication. Morespecifically, the present invention relates to an apparatus and methodof fabrication of electrically programmable storage cells withsource/drain diffusions that allow high level programming voltages.

BACKGROUND ART

Semiconductor memory devices are typically classified into volatilememory devices and non-volatile memory devices. Volatile memory devicesare subdivided into dynamic random access memories (DRAMs) and staticrandom access memories (SRAMs). Non-volatile memory types include maskread-only memories (MROMs), programmable read-only memories (PROMs),erasable programmable read-only memories (EPROMS), and electricallyerasable programmable read-only memories (EEPROMs). Additionally, flashEEPROMs are advantageous as mass storage devices because theirintegration density is high compared with conventional EEPROMs.

Non-volatile semiconductor memories have attained broad utilization dueto an ability to retain data within a device, even after power has beensuspended. EEPROMs are non-volatile semiconductor memories that possesthese abilities and additionally are able to store data by electricallyerasing and writing storage, devices. This programming process can berepeated over hundreds and thousands of cycles.

Frequently, it would be convenient to be able to mix integrated circuitdevice types, such as EEPROMs with other memory devices or bipolar andMOSFET (BiCMOS) circuits onto a single integrated circuit chip. Howeverdue to the inherently low breakdown voltage (approximately 10 volts orless) of the typical wells used in these devices and the need for a highprogramming voltage of a flash memory device (approximately 11 to 15volts), there has been no simple and economical way to integrate thesetwo device types into a single integrated circuit.

DISCLOSURE OF INVENTION

The present invention relates to an EEPROM memory cell that uses asilicon-germanium/silicon (SiGe/Si) film or alternatively, a SiGe/Sifilm in combination with an emitter polysilicon (Epoly) film forfabricating shallow CMOS source/drain regions or bipolar emitter regionsto increase a breakdown voltage of the wells. The source/drain andemitter regions are fabricated to be approximately 100 nanometers (nm)or 0.1 micrometers (μm) in depth with a breakdown voltage with respectto a well of approximately 14 volts or more. Typical dopantconcentrations for an n-type lightly doped diffusion (NLDD) is 1E17/cm³,for a p-type lightly doped diffusion (PLDD) is 1E18/cm³, and for aburied n⁺ dopant region (BN⁺) is 5E17/cm³. A typical well depth isapproximately 3 μm.

Within a combined Bipolar-Complementary Metal Oxide Semiconductor(BiCMOS) process, conventional source/drain diffusions are relativelydeep, approximately 0.2 micrometers. This depth of source/draindiffusions means less separation is available for depletion layerisolation from the well than that provided by the shallow source/draindiffused regions of the present invention. A typical breakdown voltageof a well in a BiCMOS process is approximately 10 volts. Due to theincreased breakdown voltage achieved with the present invention, EEPROMmemory cells can be produced in wells used in the BiCMOS process.

The present invention is a method of fabricating an integrated circuitby producing an n-well into an uppermost surface of a semiconductorsubstrate, doping a source dopant region and a drain dopant region, anddoping a combination drain/source dopant region. The well and dopedregions are all fabricated within an uppermost surface of thesemiconducting substrate. The drain and source dopant regions, and thecombination drain/source dopant region are all doped with acceptorsites. A portion of a gate region is also doped to have a higherconcentration of acceptor sites than either of the drain or sourcedopant regions or the combination drain/source region. The gate regionis doped to be electrically coupled to the drain region in order tofacilitate programming of the memory transistor of the EEPROM cell.Silicon-germanium and then polysilicon are deposited over the sourcedopant region and the drain dopant region to form epitaxialsilicon-germanium/silicon regions. The silicon-germanium/silicon regionsare fabricated with a higher acceptor concentration that either thedrain or the source dopant regions or the combination drain/sourceregion. At least one, PMOS transistor is fabricated from the source andcombination drain/source dopant regions and the PMOS transistor isconfigured to serve as a select transistor in a memory cell. At leastone additional PMOS transistor is fabricated from the drain and thecombination drain/source dopant regions, with the additional PMOStransistor configured to serve as a memory transistor in the memorycell.

Additionally, the present invention is also a method of fabrication ofan EEPROM cell having PMOS and NMOS transistors that have similarbenefits to those of the at least two PMOS transistor version describedsupra. In a manner similar to that described supra, an integratedcircuit is fabricated by producing an n-well into a portion of anuppermost surface of a semiconductor substrate. Additionally, a p-wellis produced into at least a portion of the remaining extent of theuppermost surface of the semiconductor substrate. Doping a first sourcedopant, region and a first drain dopant region in the n-well forms aselect transistor. Doping a second source dopant region and a seconddrain dopant region in the p-well forms a memory transistor. The firstdopant regions are acceptor sites and the second dopant regions aredonor sites. A portion of a gate region within the p-well is also doped.The gate region has a higher concentration of donor sites than eitherthe second drain or the second source region. The gate region is dopedto be electrically coupled to the second drain region in order tofacilitate programming of the memory transistor of the EEPROM cell.

The present invention is also an electronic integrated circuitfabricated onto a single integrated circuit chip. The integrated circuitchip includes a first field effect transistor (FET) configured as aselect transistor, a second FET configured to operate as a memorytransistor and coupled to the first transistor, and at least one NPN orPNP transistor. The second FET is configured to have a programmingvoltage of about 9 to 15 volts. For a PMOS memory transistor with a PMOSselect transistor, the programming voltage is about 12 to 15 volts. Foran NMOS memory transistor with a PMOS select transistor, the programmingvoltage is about 9 to 11 volts. The first FET and the second FET areconfigured to operate as an EEPROM cell.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a cross-section of a PMOS-PMOS EEPROM storage cell withSiGe film application windows exposed.

FIG. 2 shows a cross-section of a PMOS-PMOS EEPROM storage cell withSiGe film applied.

FIG. 3 shows a cross-section of a PMOS-PMOS EEPROM storage cell withSiGe film wherein the SiGe film is doped with a high concentration ofboron.

FIG. 4 shows a cross-section of a PMOS-PMOS EEPROM storage cell withSiGe film and boron diffused into source/drain regions and metalcontacts applied.

FIG. 5 shows a cross-section of a PMOS-NMOS EEPROM storage cell withfilm application windows exposed.

FIG. 6 shows a cross-section of a PMOS-NMOS EEPROM storage cell withSiGe film application in a PMOS select device and an NMOS storage deviceutilizing standard n-type source/drain region diffusions.

FIG. 7 shows a cross-section of a PMOS-NMOS EEPROM storage cell withSiGe film application in a PMOS select device and an NMOS storage deviceutilizing n-Epoly source/drain regions.

BEST MODE FOR CARRYING OUT THE INVENTION

An electronic memory device of the present invention has source/drainjunctions with a relatively high (e.g. about 14 volts or approximately12-15 volts) breakdown voltage with respect to a well for a PMOS-PMOStype memory cell. The breakdown voltage of a well on a typical bipolarprocess is only about 10 volts. A lower well breakdown voltage isattributed to a deep (e.g., approximately 200 nm or greater (0.2 μm))source/drain doped region. For a PMOS select device and an NMOS memorydevice a programming voltage of approximately 9-11 volts is produced.Using a silicon-germanium/silicon film of the present invention tofabricate source/drain regions of an MOS device results in shallowjunctions and a resulting higher breakdown voltage. Therefore, the highbreakdown voltage allows the present invention to be fabricated in anintegrated CMOS/Bipolar (i.e., BiCMOS) line, allowing both EEPROM andBiCMOS devices to be formed in an integrated circuit.

With respect to FIGS. 1-7, exemplary embodiments of the presentinvention are described according to the following process steps. FIG. 1includes a cross-section 100 of doped regions used to create electronicdevice structures such as an EEPROM cell and an NPN transistor. FIG. 1further includes a base substrate 105, a doped n-well 110, a lightlydoped memory transistor drain doped region 124, a memory transistor gatedoped region 125, a lightly-doped drain/source doped region 122, and alightly-doped select transistor source doped region 120. Processes wellknown to one of skill in the art form all doped regions. Alternatively,the n-well 110 may be an epitaxial deposition layer with n-type doping.

The base substrate 105 is frequently a silicon wafer. In thisembodiment, the silicon wafer contains a p-type dopant. Alternatively,another elemental group IV semiconductor or compound semiconductor(e.g., groups III-V or II-VI) may be selected for base substrate 105.For a p-type silicon base substrate 105, the epitaxial deposition layerand an implant form an n-well 110 containing a donor-type dopant. Thememory transistor drain doped region 124 and the drain/source dopedregion 122 are implanted with a p-type dopant and the memory transistorgate doped region 125 is a buried p-type (p+). The memory transistorgate doped region 125 is used to form a bottom plate of a couplingcapacitor and a heavily-doped region for an overlying tunnel diodewindow (TDW), discussed in more detail infra.

In a specific exemplary embodiment, the memory drain doped region 124,the memory gate doped region 125, the drain/source doped region 122, andthe select source doped region 120 are all produced by an ionimplantation step followed by a drive-in step (e.g., by rapid thermalannealing (RTA)) to have a junction depth of approximately 100 nm (0.1μm).

FIG. 1 further includes a cross-section of a film stack applied over thedopant regions. The film stack includes a gate oxide layer 161, a tunneldiode window (TDW) 135, a memory transistor gate polysilicon layer 130and a select transistor gate poly silicon layer 140. The gate oxidelayer 161 is either thermally grown or deposited, for example, bychemical vapor deposition (CVD). After the gate oxide layer 161 is grownor deposited, and prior to deposition of the polysilicon layer 130, anopening is made in the gate oxide layer 161 to form, inter alia, the TDW135. The opening is made by applying a photoresist layer (not shown),photolithographically exposing the photoresist layer, and developing andetching the photoresist layer to form an etch mask for the TDW 135.Subsequently, the TDW 135 may be etched through various etchingtechniques, such as a wet etch (e.g., a hydrofluoric acid etch, such ascontained in a standard buffered oxide etch, or orthophosphoric acid) ordry etch (e.g., reactive-ion etch (RIE)) techniques. A brief thermaloxidation step is performed to grow a thin tunnel oxide of the TDW 135.

In a specific exemplary embodiment, the gate oxide layer 161 isthermally grown and is 18 nm-20 nm (180 Å-200 Å) thick and the oxide ofthe TDW 135 is 7 nm (70 Å) thick.

With further reference to FIG. 1, the polysilicon layer is patterned byexposing, developing, and etching an overlaying photoresist layer (notshown), and etching the polysilicon layer; techniques well known to oneskilled in the art. After etching, the polysilicon layer forms a memorytransistor gate polysilicon area 130 and a select transistor gatepolysilicon area 140.

A nitride layer (not shown) is deposited over the memory transistor gatepolysilicon area 130 and the select transistor gate polysilicon area140. The nitride layer is patterned and dry etched (e.g., by RIE)forming nitride spacers 115 surrounding the gate polysilicon areas 130and 140. Depending on a selectivity of an etchant chosen for use in the,RIE process, there may be some over-etching of the nitride layer andinto the gate oxide layer 161. If the process contemplates integratedCMOS/Bipolar technologies, discussed supra, formation of the nitridespacers 115 ends the CMOS process steps.

The bipolar device formation process begins with a depositions of a CVDoxide 160 and a second polysilicon layer 165. A photoresist layer (notshown) overlaying the CVD oxide 160 and the second polysilicon layer165, is exposed, developed, and etched. The etched photoresist layerserves as an etch mask for etching the CVD oxide 160 and the secondpolysilicon layer 165, producing silicon-germanium (SiGe) windows 155.

With reverence to FIG. 2, a SiGe/Si film 205 is deposited into the SiGewindows (i.e., over the memory transistor drain doped region 124 and theselect transistor source doped region 120 (FIG. 1)) and onto surroundingregions.

With regard to FIG. 3, the SiGe/Si film 205 is doped, for example, withboron, producing a doped SiGe/Si film 305. The doping is followed byapplying an additional photoresist layer (not shown). Photolithographicexposure, development, and etching of the photoresist and underlyingSiGe/Si film 305 produces, inter alia, the source/drain contact regions457 (FIG. 4) for the memory and select devices.

With regard to FIG. 4, the boron implant film 305 is etched and forms ashallow doped region 437 within the source/drain contact dopant regions457. These shallow doped regions have an acceptor concentration higherthan that of the surrounding doping of the drain doped region 124 andthe source doped region 120. This high acceptor concentration at ashallow depth produces a characteristic of high breakdown voltage withrespect to the well of the present invention. This is accomplished bythe shallow doping of high concentration 437 at each contact dopantregion 457 allowing greater separation for forming a depletion layerisolation from the doped n-well 110.

With further reference to FIG. 4, metallic contacts 467 are formed tocouple to the source/drain contact regions 457. Processes well known toa skilled artisan form the metallic contacts 467. The processes brieflyinvolve, for example, depositing a CVD dielectric layer over theexisting structures, patterning and etching vias in the dielectric (oneabove each source/drain contact region 457), depositing a titaniumnitride (TiN) or titanium (Ti) liner on interior walls of the via, anddepositing a tungsten (W) or copper (Cu) plug within each lined via.

With regard to FIG. 5 an EEPROM memory cell has a PMOS transistor 501used as a select device and an NMOS transistor 503 as a memory device.The PMOS transistor is formed from a polysilicon gate 530 along with adoped source region 520) and a doped drain region 522 within an n-wellregion 510. The n-well region is applied upon an epitaxially layer (notshown) which is grown upon a lightly doped (e.g., 7E14/cm³, p-type)semiconductor substrate 505 material. The NMOS transistor 503 resideswithin a p-type well (p-well) 513 and is isolated from the n-well 510and the PMOS transistor. A shallow trench isolation (STI) structure 555is used for this electrical separation.

The NMOS transistor 503 formation of the memory device is similar to thePMOS formation of a memory transistor described supra. Briefly, thestructure of the NMOS memory transistor 503 is a source doped region525, a drain doped region 523, a gate doped region 528 coupled to thedrain doped region 523 forming a bottom plate of a TDW 538, apolysilicon gate 533, a gate oxide 561, and nitride spacers 518surrounding the polysilicon gate 533.

Similar to the fabrication of the PMOS-PMOS EEPROM cell (FIGS. 1-4),described supra, the PMOS-NMOS structure is covered with a film of CVDoxide 560 and a second polysilicon layer 565. A photoresist layer (notshown) overlaying the CVD oxide 560 and the second polysilicon layer565, is exposed, developed, and etched. The etched photoresist layerservers as an etch mask for etching the CVD oxide 560 and the secondpolysilicon layer 565, producing a first SiGe window 556 for the PMOStransistor 501 and a second SiGe window 558 over the NMOS memorytransistor 503 for either a SiGe film or an emitter polysilicon film, tobe described infra.

With reference to FIG. 6, an exemplary embodiment of a PMOS-NMOS EEPROMstorage cell has SiGe windows 556, 558 (FIG. 5) deposited with a SiGe/Sifilm. The PMOS transistor 501 is doped with a high concentration ofp-type material, for example boron, into the source region 648 and drainregion 647. The NMOS transistor 503 is doped with a high concentrationof n-type material, for example arsenic, into the source region 658 anddrain region 657. As with the PMOS-PMOS embodiment (FIGS. 1-4),discussed supra, a shallow high concentration region 653 is formedwithin the source/drain doped regions 647, 648, 657, and, 658, whichcomes from the high concentration dopants, of the applied films (notshown). This high concentration at a shallow depth produces thecharacteristic of high breakdown voltage with respect to the wells 510,513 of the present invention.

In reference to FIG. 7, another exemplary embodiment of a PMOS-NMOSEEPROM storage cell has the SiGe windows 556 (FIG. 5) deposited with aSiGe/Si film. The PMOS transistor 501 is doped with a high concentrationof p-type material, for example boron, over the source region 648 anddrain region 647. The windows over the NMOS source/drain 558 (FIG. 5)are e-poly windows wherein an emitter polysilicon film (not shown) isapplied and doped, for example, with a high concentration of arsenic,followed by applying an additional photoresist layer (not shown). Ashallow high concentration region 753 is formed within the source/draindoped regions 647, 648, 757, and 758, which comes from the highconcentration dopants of the applied films. This high concentration at ashallow depth produces the characteristic of high breakdown voltage withrespect to the wells 510, 513 of thee present invention.Photolithographic exposure, development, and etching of the photoresistand underlying emitter polysilicon film produces, inter alia, the sourcecontact region 758 and the drain contact region 757 of the NMOStransistor 503.

Metallization steps (not shown), known to one of skill in the art, willprovide actual connection terminals in later process steps for the CMOSand bipolar devices. Following the completion of major processing stepsreferenced in FIGS. 4, 6, and 7, techniques well known to a skilledartisan are used to perform, for example, additional metallization,electronic-test, and packaging steps to complete the semiconductormemory cell device and one or more bipolar devices. Bipolar devices, forexample, are formed by stacking SiGe and emitter poly films over ann-well region. The SiGe and emitter poly films form the base andemitter, respectively. An n-well region forms the collector of an npndevice, for instance.

Although process steps and techniques are shown and described in somedetail, a skilled artisan will recognize that other techniques andmethods may be utilized which are still included within a scope of thepresent invention. For example, there are frequently several techniquesused for depositing a film layer (e.g., chemical vapor deposition)plasma-enhanced vapor deposition, epitaxial deposition, atomic layerdepositions, etc.). Although not all techniques are amenable to all filmtypes described herein, one skilled in the art will recognize thatmultiple methods for depositing a given layer and/or film type may beused. Additionally, various techniques may be used to dope regions in asemiconductor. Although implantation has been described in the exemplaryembodiments, one skilled in the art realizes that other dopingprocedures, such as diffusion, could be substituted or combined with theimplantation procedures described herein. Further, the overall layouthas been described in terms of horizontally disposed CMOS and bipolardevices. However, a skilled artisan will recognize the present inventiondisclosed is readily applicable to a formation of vertically disposeddevices as well. Therefore, the scope of the present invention shallonly be limited by a scope of the appended claims.

1. An electronic integrated circuit comprising: a first PMOS transistorconfigured to control an operation of a memory transistor; a second PMOStransistor configured to operate as a memory transistor with a floatingprogramming gate and coupled to the first PMOS transistor, the secondPMOS transistor configured to have a programming voltage from 12 to 15volts, the first PMOS transistor and the second PMOS transistorconfigured to operate as an EEPROM cell; and at least one bipolardevice, the at least one bipolar device being in electricalcommunication with the select transistor and the memory transistor andconfigured to have a breakdown voltage greater than or equal to theprogramming voltage of the NMOS transistor.
 2. The electronic integratedcircuit of claim 1, wherein the first PMOS transistor comprises a sourcedopant region and a combination drain/source dopant region, wherein allthe dopant regions are doped to a depth of about 100 nm.
 3. Theelectronic, integrated circuit of claim 1, wherein the second PMOStransistor comprises a combination drain/source dopant region, a gatedopant region, and a drain dopant region that are all doped to a depthof about 100 nm, the second PMOS transistor further comprises a floatingprogramming gate located in proximity to the gate dopant region.
 4. Theelectronic integrated circuit of claim 3, wherein the gate dopant regionis coupled to the drain dopant region.
 5. The electronic integratedcircuit of claim 1, wherein the second PMOS transistor further comprisesa tunnel diode window.
 6. The electronic integrated circuit of claim 5,wherein an oxide in the tunnel diode window is about 7 nm thick.
 7. Anelectronic integrated circuit comprising: a PMOS transistor configuredto control an operation of a memory transistor; an NMOS transistorconfigured to operate as a memory transistor with a floating programminggate and coupled to the PMOS transistor, the NMOS transistor configuredto have a programming voltage of 9 to 11 volts, the PMOS transistor andthe NMOS transistor configured to operate as an EEPROM cell; and atleast one bipolar device, the at least one bipolar device being inelectrical communication with the select transistor and the memorytransistor and configured to have a breakdown voltage greater than orequal to the programming voltage of the NMOS transistor.
 8. Theelectronic integrated circuit of claim 7, wherein the PMOS transistorcomprises a PMOS drain dopant region and a PMOS source dopant region,which are all doped to a depth of about 100 nm.
 9. The electronicintegrated circuit of claim 7, wherein the NMOS transistor comprises anNMOS drain dopant region, an NMOS gate dopant region, and an NMOS sourcedopant region, wherein all the dopant regions are doped to a depth ofabout 100 nm, the NMOS transistor further comprises a floatingprogramming gate located in proximity to the gate dopant region.
 10. Theelectronic integrated circuit of claim 9, wherein the gate dopant regionis coupled to the second drain dopant region.
 11. The electronicintegrated circuit of claim 7, wherein the PMOS transistor comprises afirst drain dopant region and a first source dopant region, the NMOStransistor comprises a second drain dopant region, a gate dopant region,and a second source dopant region, wherein the first drain dopant regionis coupled to the second drain dopant region, the PMOS transistor andthe NMOS transistor configured to operate as an EEPROM cell.
 12. Theelectronic integrated circuit of claim 7, wherein the NMOS transistorfurther comprises a tunnel diode window.
 13. The electronic integratedcircuit of claim 12, wherein an oxide in the tunnel diode window isabout 7 nm thick.